Monte Carlo simulations of strained Si/SiGe-OI nMOSFETs

• Main Authors: A. Yangthaisong, T. Osotchan
• Other Authors: Ubon Rajathanee University
• Format: Conference or Workshop Item
• Published: 2018
• Subjects: Engineering
• Online Access: https://repository.li.mahidol.ac.th/handle/123456789/23236
• Institution: Mahidol University

The motivation for research into n-type strained-Si/SiGe-on-insulator metal-oxide field effect transistors (SiGe-OI MOSFETs) is to take advantage of both the enhancement of electron transport properties due to strain and the mass production of advanced CMOS technology. Two dimensional self-consistent ensemble Monte Carlo simulation has been used to provide a description of the steady and transient charge transport in a strained-Si/SiGe-OI nMOSFET with 55 nm gate length. The simulated device is similar to that investigate experimentally by the IBM group. The simulation provides information on the microscopic details of the carrier behavior, including carrier velocity, kinetic energy, and carrier density, as a function of position in the device. Detailed time-dependent voltage signal analysis has been carried out to test the device response and derive the frequency bandwidth, which has been compared with the result of an identical analysis performed on a conventional planar geometry silicon-on-insulator (SOI) nMOSFET of similar dimensions and doping. A sine voltage pulse is applied to the gate and the resulting drain current and gate currents used to calculate the current gain as a function of frequency. Figure 5 shows that the current gain of Si/SGOI MOSFET could have an intrinsic cut-off frequency approaching 200 = 10 GHz, a 50 % improvement over the unstrained device. © 2006 IEEE.