Simulation of multiple gate FinFET device gate capacitance and performance with gate length and pitch scaling

• Main Authors: Zhao, H., Agrawal, N., Javier, R., Rustagi, S.C., Jurczak, M., Yeo, Y.-C., Samudra, G.S.
• 其他作者: ELECTRICAL & COMPUTER ENGINEERING
• 格式: Conference or Workshop Item
• 出版: 2014
• 主題: 3D simulation; Capacitance; FinFET; Multi-gate; Scaling
• 在線閱讀: http://scholarbank.nus.edu.sg/handle/10635/71782
• 機構: National University of Singapore

10.1109/SISPAD.2006.282883