Ultra-narrow silicon nanowire gate-all-around CMOS devices: Impact of diameter, channel-orientation and low temperature on device performance

• Main Authors: Singh, N., Lim, F.Y., Fang, W.W., Rustagi, S.C., Bera, L.K., Agarwal, A., Tung, C.H., Hoe, K.M., Omampuliyur, S.R., Tripathi, D., Adeyeye, A.O., Lo, G.Q., Balasubramanian, N., Kwong, D.L.
• 其他作者: ELECTRICAL & COMPUTER ENGINEERING
• 格式: Conference or Workshop Item
• 出版: 2014
• 在線閱讀: http://scholarbank.nus.edu.sg/handle/10635/84334
• 機構: National University of Singapore

10.1109/IEDM.2006.346840