An automatic mapping from Statecharts to Verilog

Lecture Notes in Computer Science

محفوظ في:
التفاصيل البيبلوغرافية
المؤلفون الرئيسيون: Tran, V.-A.V., Qin, S., Chin, W.N.
مؤلفون آخرون: SINGAPORE-MIT ALLIANCE
التنسيق: Conference or Workshop Item
منشور في: 2013
الوصول للمادة أونلاين:http://scholarbank.nus.edu.sg/handle/10635/43326
الوسوم: إضافة وسم
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المؤسسة: National University of Singapore
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spelling sg-nus-scholar.10635-433262024-11-12T18:27:48Z An automatic mapping from Statecharts to Verilog Tran, V.-A.V. Qin, S. Chin, W.N. SINGAPORE-MIT ALLIANCE COMPUTER SCIENCE Lecture Notes in Computer Science 3407 187-203 2013-07-23T09:31:03Z 2013-07-23T09:31:03Z 2005 Conference Paper Tran, V.-A.V.,Qin, S.,Chin, W.N. (2005). An automatic mapping from Statecharts to Verilog. Lecture Notes in Computer Science 3407 : 187-203. ScholarBank@NUS Repository. 03029743 http://scholarbank.nus.edu.sg/handle/10635/43326 NOT_IN_WOS Scopus
institution National University of Singapore
building NUS Library
continent Asia
country Singapore
Singapore
content_provider NUS Library
collection ScholarBank@NUS
description Lecture Notes in Computer Science
author2 SINGAPORE-MIT ALLIANCE
author_facet SINGAPORE-MIT ALLIANCE
Tran, V.-A.V.
Qin, S.
Chin, W.N.
format Conference or Workshop Item
author Tran, V.-A.V.
Qin, S.
Chin, W.N.
spellingShingle Tran, V.-A.V.
Qin, S.
Chin, W.N.
An automatic mapping from Statecharts to Verilog
author_sort Tran, V.-A.V.
title An automatic mapping from Statecharts to Verilog
title_short An automatic mapping from Statecharts to Verilog
title_full An automatic mapping from Statecharts to Verilog
title_fullStr An automatic mapping from Statecharts to Verilog
title_full_unstemmed An automatic mapping from Statecharts to Verilog
title_sort automatic mapping from statecharts to verilog
publishDate 2013
url http://scholarbank.nus.edu.sg/handle/10635/43326
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