Automated scripts for testing verilog designs with iVerilog

• 主要作者: Ng, Gary Jia Hao
• 其他作者: Suhaib A Fahmy
• 格式: Final Year Project
• 語言: English
• 出版: 2015
• 主題: DRNTU::Engineering::Computer science and engineering
• 在線閱讀: http://hdl.handle.net/10356/62552
• 機構: Nanyang Technological University

Writing a testbench to test Verilog designs is a tedious process. The user is required to first have a very clear understanding of the design specifications. After which, a test plan can then be devised to document the test bench architecture and scenarios in detail. Undergraduates often lack the re...