Test bench modeling and characterization for fine pitch wafer level packaged devices

• Main Authors: Jayabalan, J., Mihai, R.D., Tan, J.P.H., Iyer, M.K., Leong, O.B., Seng, L.M.
• 其他作者: ELECTRICAL & COMPUTER ENGINEERING
• 格式: Conference or Workshop Item
• 出版: 2014
• 主題: Fine pitch; Interconnect modeling; Multi-gigahertz test; Wafer level package
• 在線閱讀: http://scholarbank.nus.edu.sg/handle/10635/71958

Proceedings of 6th Electronics Packaging Technology Conference, EPTC 2004