Automated scripts for testing verilog designs with iVerilog

• المؤلف الرئيسي: Ng, Gary Jia Hao
• مؤلفون آخرون: Suhaib A Fahmy
• التنسيق: Final Year Project
• اللغة: English
• منشور في: 2015
• الموضوعات: DRNTU::Engineering::Computer science and engineering
• الوصول للمادة أونلاين: http://hdl.handle.net/10356/62552
• المؤسسة: Nanyang Technological University

Writing a testbench to test Verilog designs is a tedious process. The user is required to first have a very clear understanding of the design specifications. After which, a test plan can then be devised to document the test bench architecture and scenarios in detail. Undergraduates often lack the re...