Low power CMOS circuits

• المؤلف الرئيسي: Teo, Kok Chin
• مؤلفون آخرون: Lau Kim Teen
• التنسيق: Final Year Project
• اللغة: English
• منشور في: 2014
• الموضوعات: DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
• الوصول للمادة أونلاين: http://hdl.handle.net/10356/61400
• المؤسسة: Nanyang Technological University

Basic building block of CMOS integrated circuit like inverter, NAND, Latch and Full Adder will be simulated under low voltage condition using the Cadence software. This is an attempt to study the operations of these circuits when voltage is lowered to reduce the power consumption. Results will then...