VLSI implementation of Reed Solomon encoder and decoder chip

VLSI implementation of Reed Solomon encoder and decoder chip

This report represents the VLSI design implementation of the Reed Solomon Encoder and Decoder. The overall architecture, design, simulation and synthesis of the Reed Solomon Encoder and Decoder, as well as the internal modules are discussed in detail.

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書目詳細資料
主要作者:	Lau, Luh Chyuan.
其他作者:	Ho, Duan Juat
格式:	Theses and Dissertations
出版:	2008
主題:	DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits
在線閱讀:	http://hdl.handle.net/10356/4561
標簽:	添加標簽沒有標簽, 成為第一個標記此記錄!

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