Design of a low-voltage input-output rail-to-rail CMOS buffer

The objective of this project is to design a low-voltage rail-to-rail input/output CMOS buffer, which is able to work under a supply voltage of 1.8V typical and remain in operation even at l.2V or lower in the worst case for use in bond pad designs. The circuit is designed and simulated using Caden...

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書目詳細資料
主要作者: Chai, Yanjie
其他作者: Chen Tupei
格式: Theses and Dissertations
語言:English
出版: 2010
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在線閱讀:http://hdl.handle.net/10356/41770
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