Optional layout of input / output protection devices

• Main Authors: Liu, Po Ching., Siek, Liter.
• 其他作者: School of Electrical and Electronic Engineering
• 格式: Research Report
• 出版: 2008
• 主題: DRNTU::Engineering::Electrical and electronic engineering::Electronic apparatus and materials
• 在線閱讀: http://hdl.handle.net/10356/2717
• 機構: Nanyang Technological University

This project was initiated for the effective design and layout of input protection devices. Scope of this work includes setting up prototype ESD testing environment, studying the layout of commercial chips and the ESD threshold voltages, then test our own design on the chip fabricated.