Design of a >500MHz current starving VCO/DLL with low phase noise for digital PWM control

• المؤلف الرئيسي: Chua, Dillon Yu Ze
• مؤلفون آخرون: Siek Liter
• التنسيق: Final Year Project
• اللغة: English
• منشور في: Nanyang Technological University 2023
• الموضوعات: Engineering::Electrical and electronic engineering
• الوصول للمادة أونلاين: https://hdl.handle.net/10356/168475
• المؤسسة: Nanyang Technological University

The fundamental building blocks of delay locked loops is the chain of delay elements that forms the delay lines. They are used in many VLSI circuits that require a clock distribution network. There are two popular methods implemented in a delay line. Namely, shunted capacitor delay elements an...