Design and analysis of a low-noise regulated negative voltage generator system
This thesis presents the design and analysis of a generic, low-noise regulated negative voltage generator, with wide tuning range and moderate driving capability. The highly integrated solution comprises of a multi-phase clock generator, fullyintegrated charge-pump and a regulator block while requir...
Saved in:
主要作者: | Khanna, Devrishi |
---|---|
其他作者: | Boon Chirn Chye |
格式: | Thesis-Doctor of Philosophy |
語言: | English |
出版: |
Nanyang Technological University
2020
|
主題: | |
在線閱讀: | https://hdl.handle.net/10356/144061 |
標簽: |
添加標簽
沒有標簽, 成為第一個標記此記錄!
|
機構: | Nanyang Technological University |
語言: | English |
相似書籍
-
Design of low-voltage low-power low-noise folded-cascode CMOS op-amp with class AB output stage
由: Ng, Chen Hui
出版: (2023) -
Design of low drop-out linear voltage regulator
由: Zhao, Xin.
出版: (2009) -
Design of a low-drop-out voltage regulator
由: Ong, Jian Cheng.
出版: (2009) -
Resistor-less low dropout voltage regulator
由: Lee, Han Jian
出版: (2018) -
A design of an all-MOS-transistor low-power low-voltage LDO with an embedded voltage reference
由: He, Junsen
出版: (2020)