Integrated platform for design and verification of digital FIR filters - Sharma Udit (2008)
This work aimed at creating a unified platform to automate the generation of VHDL codes for the physical synthesis of FIR filters in both direct and transposed direct form filters. The aim was to provide designers and researchers with a tool to analyze the physical performances of different filter solutions in terms of VLSI area, delay and power consumption. Many benchmark filters were collected for such evaluation. This platform also performs a functional verification of the VHDL codes by running parallel simulations in a simulator and comparing the final output with its own response to randomly generated stimuli, thereby avoiding manual supervision.