Design implementation low energy fast fourier transform/inverse fast fourier transform (FFT/IFFT) processor based on asynchronous-logic - Chong, Kwen Siong (2008)
This thesis pertains to circuit designs using the promising asynchronous-logic (async) approach as opposed to the prevalent synchronous-logic (sync) approach, with emphases on low voltage operation and low energy dissipation. The circuits designed herein span from microcells and macrocells to a complete 128-point radix-2 decimation-in-time Fast Fourier Transform/Inverse Fast Fourier Transform (FFT/IFFT) processor for energy-critical audio applications, including hearing aids. The novel microcells and macrocells include a Latch Adder, a Latch Accumulator, a Type-gamma 2-bit carry completion sensing adder, a latch controller, a 16?16-bit Booth array-based multiplier core, a 16?16-bit ‘Control-Multiplier’, and a 128?16-bit memory macrocell. The novelties of these designs include the incorporation of different functional features and reduced spurious switching, resulting in increased versatility, compactness, and lower energy dissipation. By means of appropriate async design techniques and proposed microcells and macrocells, the async FFT/IFFT processor is demonstrated to feature superior energy attributes over its sync counterpart.