Software defined network on chip - Gopalakrishnan, Sharan (Nanyang Technological University, 2025)
Network-on-Chip (NoC) architectures have become a significant field of due to its potential in magnifying the overall performance of Heterogeneous Computing Systems (HCS). With increasingly resource-heavy and complex workloads on the rise, optimizing NoCs will greatly aid in efforts to improve performance metrics. The publicly available Gem5 simulator allows for the creation and testing of custom NoC architectures for observation. One such architecture whose performance metrics we wish to obtain and study is the ArSMART architecture, developed by the ntuliuteam. Ideally, the goal would be to run applications and workloads over the ArSMART NoC, so that we can see the difference in performance when using this architecture over other standard NoCs. This report mainly attempts to outline the challenges faced while attempting to run certain benchmark suites such as PARSEC over the ArSMART NoC in the Gem5 simulator. It documents the challenges faced while attempting to with a custom ArSMART NoC in Gem5. Despite extensive efforts, persistent simulation errors prevented obtaining performance metrics. However, this work provides an analysis of failed methodologies and debugging strategies to guide future researchers in overcoming similar obstacles. Alternative solutions such as the usage of synthetic task graph files as substitutes are also discussed. By documenting these methodologies that were taken, this report aims to provide a helpful guide to refine their approaches and avoid hitting similar stumbling blocks.