An unclocked analog-to-digital converter

• Main Authors: Siek, Liter, Graham, Rigby
• 其他作者: School of Electrical and Electronic Engineering
• 格式: Conference or Workshop Item
• 語言: English
• 出版: 2021
• 主題: Engineering::Electrical and electronic engineering; High Speed ADC; Unclocked A/D Technique; Analog-to-Digital Converter
• 在線閱讀: https://trove.nla.gov.au/work/18049131; https://hdl.handle.net/10356/152451

An unclocked A/D technique using a serial chain of comparators in its speed limiting path is described. The design fabricated in 2 μm double-metal single-polysilicon p-well CMOS technology occupies an area of 1.67 mm×1.67 mm, produces an 8-bit conversion in<1 μs and consumes a power of 40 mW.