A 12-bit branching time-to-digital converter with power saving features and digital based resolution tuning for PVT variations

• Main Authors: Teh, Jian Sen, Siek, Liter
• 其他作者: School of Electrical and Electronic Engineering
• 格式: Article
• 語言: English
• 出版: 2021
• 主題: Engineering::Electrical and electronic engineering; Time-to-Digital Converter; Bridging Capacitors; Branching
• 在線閱讀: https://hdl.handle.net/10356/152448

This paper presents a 12-bit branching Time-to-Digital converter (TDC) fabricated in a 40 nm CMOS technology. It composes of a 6-bit coarse counter TDC, and a 6-bit fine TDC. The fine TDC utilizes a proposed branching technique to interpolate between the phases of a 16-stage gated ring oscillator, i...