, D., & , I. B. S. (2009). Implementasi tapis digital finite impulse response (FIR) berbasis FPGA (Field Programmable Gate Arrays). [Yogyakarta] : Universitas Gadjah Mada.
Chicago Style Citation, DERMAWAN, and Ir. Bambang Sutopo. Implementasi Tapis Digital Finite Impulse Response (FIR) Berbasis FPGA (Field Programmable Gate Arrays). [Yogyakarta] : Universitas Gadjah Mada, 2009.
MLA引文, DERMAWAN, and Ir. Bambang Sutopo. Implementasi Tapis Digital Finite Impulse Response (FIR) Berbasis FPGA (Field Programmable Gate Arrays). [Yogyakarta] : Universitas Gadjah Mada, 2009.
警告：這些引文格式不一定是100％准確.